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Archive-name: dec-faq/pdp8-models
Last-modified: Oct 1, 2000

Frequently Asked Questions about DEC PDP-8 models and options.

	By Douglas Jones, jones@cs.uiowa.edu
	(with help from many folks)

Sites known to carry reasonably current FTPable copies of this file:

	ftp://rtfm.mit.edu/pub/usenet/alt.sys.pdp8
        ftp://ftp.uu.net/usenet/news.answers/dec-faq
	ftp://src.doc.ic.ac.uk:/pub/usenet/news.answers/alt.sys.pdp8

Reasonably current automatic translations of this document to HTML format
for the World Wide Web are available from:

	http://www.faqs.org/faqs/dec-faq/
	http://www.cs.ruu.nl/wais/html/na-dir/dec-faq/.html

An obsolete version of this file is available on the Walnut Creek USENET
FAQ CDROM; another version will be published as part of the FAQbook by
Pamela Greene et al.

This posting conforms to RFC1153 USENET digest format (with exceptions due
to the fact that it is not really a digest).

The purpose of this document is to supplement the material in the primary
"Frequently Asked Questions about the PDP-8" file with more detailed
information about the hardware and options of the different models of the
PDP-8 sold by DEC.

Although this document is something of a history of the DEC PDP-8 family,
the primary purpose of this document is as a guide and general outline to
the PDP-8 models and options likely to be encountered by those involved
in collecting and restoring such systems.

Contents:

	What is a PDP-5?
	What is a PDP-8?
	What is a LINC-8?
	What is a PDP-8/S?
	What is a PDP-8/I?
	What is a PDP-8/L?
	What is a PDP-12?
	What is a PDP-8/E?
	What is a PDP-8/F?
	What is a PDP-8/M?
	What is a PDP-8/A?
	What is a VT78?
	What is a DECmate I?
	What is a DECmate II?
	What is a DECmate III?
	What is a DECmate III+?

----------------------------------------------------------------------

Subject: What is a PDP-5?

Date of introduction:  Aug 11, 1963, unveiled at WESCON.
Date of withdrawal:    early 1967.
Total production run:  116.
Price: $27,000

Technology:  The PDP-5 was built with DEC System Modules, the original
	line of transistorized logic modules sold by DEC.  The supply
	voltages were +10 and -15 volts, with logic levels of -3 (logic 1)
	and 0 (logic 0).  Logic was packaged on boards that were about
	4.75 inches high with each card mounted in a metal frame with a
	22 pin edge connector.

	Input output devices were connected to the daisy-chained I/O bus
	using military-style armored cables and connectors.  Use of
	toggle switches (as opposed to slide switches) on the front
	panel was another vestige of military-style design.

Reason for introduction:  This machine was inspired by the success of
	the CDC-160, Seymour Cray's 12 bit minicomputer, and by the
	success of the LINC, a machine that was built by DEC customers
	out of System modules.  These demonstrated that there was a
	market for a small inexpensive computer, and from the start,
	DEC's advertisements were aimed at this market.  "Now you can
	own the PDP-5 computer for what a core memory alone used to
	cost: $27,000", ran one 1964 ad.

	Ken Olson has stated that the PDP-5 was not originally meant to
	be a computer; it was designed for a company that wanted an
	automatic controller for some industrial work.  He told them
	they could make a small programmable controller instead of the
	hardwired machine they were asking for, and since they weren't
	entirely certain of the control equations they wanted to run, they
	accepted the idea. The result was the PDP-5.

Reason for withdrawal:  The PDP-8 outperformed the PDP-5, and did so for
	a lower price.

Compatability:  The core of the PDP-8 instruction set is present, but
	memory location zero is the program counter, and interrupts are
	handled differently.  The Group 1 OPR rotate instructions cannot
	be combined with IAC or CMA; this limits the ability of the
	PDP-5 to support code from later models.

The machine does not support 3 cycle data-break (DMA transfers using
	memory to hold buffer address and word-count information), so
	many later PDP-8 peripherals cannot be used on the PDP-5.  In
	addition, DMA transfers are not allowed outside the program's
	current 4K data field, severely limiting software compatability
	on systems with over 4K of memory where either interrupts or
	software initiated changes to the data field during a transfer
	would cause chaos.

Standard configuration:  CPU with 1K or 4K of memory (2K and 3K versions
	were not available).

Peripherals:
	An extended arithmetic element (EAE) was available; this was an
	I/O device, using IOT instructions to evoke EAE operations.  As
	a result, it was not compatable with the later PDP-8 EAEs.  In
	addition, machines with the EAE option had a different front
	panel from those without.

	The type 552 DECtape control and type 555 dual DECtape transports
	were originally developed for the PDP-5 and contemporaneous DEC
	systems such as the PDP-6.

	After the PDP-8 was introduced, DEC offered a bus converter that
	allowed the PDP-5 to support standard PDP-8 negibus ueripherals,
	so long as they avoided using 3-cycle data break transfers.  The
	standard 804 PDP-8 expander box was frequently sold as an
	upgrade to PDP-5 systems.

Survival:  A small number of PDP-5 systems survive, at least one in near
	operational condition!

------------------------------

Subject: What is a PDP-8?

Date of introduction:  1965 (Unveiled March 22, in New York).
Date of withdrawal:    1968.
Total production run:  1450.
Also known as:
	Classic PDP-8 (to point out lack of a model suffix)
	Straight-8 (Again, points out the lack of a model suffix)
	PCP-88, an OEM label, used by Foxboro Corporation.
        AN/GYK-6, (Army-Navy Ground-based (Y)data-processing Komputer 6)
Price: $18,000

Technology:  Mostly standard DEC R-series logic modules; these were
	originally discrete component transistor logic, but around the
	time the PDP-8 was introduced, DEC introduced the Flip Chip, a
	hybrid diode/resistor "integrated circuit" on a ceramic substrate.
	These could directly replace some of the discrete components on
	some logic modules, and DEC quickly began to refer to all R-series
	modules as flip-chip modules; they even advertised the PDP-8 as
	an integrated circuit computer.  A typical flip-chip module, the
	R111, had three 2-input nand gates and cost $14, with no price
	change from 1965 to 1970.  Some special dual height R-series
	modules were designed specifically for the PDP-8.

	S and B-series logic modules were also used; these are similar
	to their R-series cousins, but with different speed/fanout
	tradeoffs in their design.  Some logic modules have trimmers
	that must be tuned to the context, making replacement of such
	modules more complex than simply swapping boards.

	As with the system modules used in the PDP-5, the supply
	voltages were +10 and -15 volts and the logic levels were -3
	(logic 1) and 0 (logic 0).  Logic was packaged on boards that
	were 2.5 inches wide by 5 inches long.  The card edge connector
	had 18 contacts on 1/8 inch centers.  Some double height cards
	were used; these had two card edge connectors and were 5 1/8
	inches high.  Machine wrapped wire-wrap technology was used on
	the backplane using 24-gauge wire.

	The "negibus" or negative logic I/O bus used -3 and 0 volt logic
	levels in 92 ohm coaxial cable, with 9 coaxial cables bundled
	per connector card and 6 bundles making up the basic bus.  5
	(later 4) more bundles were required to support data-break (DMA)
	transfers.  The total bus length was limited to 50 feet, and bus
	termination was generally kluged in with 100 ohm resistors
	clipped or wrapped into the backplane, although a bus terminator
	card was sometimes used.  Some time after the first year of
	production, flat ribbon cable made of multiple coaxial cables
	was used, and later still, shielded flat stripline cable was used
	(but this cut the allowed bus length by a factor of two).

	Core memory was used, originally made by FERROXCUBE, with a 1.5
	microsecond cycle time, giving the machine an add time of 3
	microseconds.  4K of core occupied an aluminum box 6 inches on a
	side and needed numerous auxiliary flip-chips and for support,
	as well as an array of boards from the core vendor.  It is worth
	noting that the PDP-8 was about as fast as was practical with the
	logic technology used; only by using tricks like memory
	interleaving or pipelining could the machine have been made much
	faster.

Reason for introduction:  This machine was inspired by the success of
	the PDP-5 and by the realization that, with their new Flip-Chip
	technology, DEC could make a table-top computer that could be
	powered by a single standard wall outlet; of course, adding any
	peripherals quickly increased the power requirement!

Reason for withdrawal:  The PDP-8/I was less expensive, and after
	initial production difficulties, it equalled the performance of
	the PDP-8.

Compatability:  This machine defines the core of the PDP-8 instruction
	set, but with restrictions that were lifted on later machines.
	The Group 1 OPR instruction IAC cannot be combined with any of
	the rotate instructions.  If RAR and RAL or RTR and RTL are
	combined, the results are unpredictable (simultaneous set and
	reset of bits of AC results in metastable behavior).  The IOT 0
	instruction was used for the internal type 189 ADC, and not for
	the later CAF (clear all flags) instruction.  As a result, if
	the ADC option was not present, IOT 6004 (or microcoded
	variants) would hang the machine.

	The SWP instruction (exchange AC and MQ) never works, even if
	the extended arithmetic element is present.  This works on later
	models when the EAE is present, although it was only documented
	with the introduction of the PDP-8/E.  Finally, the EAE lacks
	the SCL (shift count load) instruction that is present on later
	models.

	On machines with 8K or more, an attempt to change the data field
	to a non-existant field caused a bizarre double-indirect and
	skip instruction execution that must be accounted for in memory
	diagnostics.

Standard configuration:  The PDP-8 was sold as a CPU with 4K of memory,
	a 110 baud current loop teletype interface and an ASR 33 Teletype.
	In addition, the standard in-cabinet logic includes support for
	the full negibus interface, including data-break (DMA) transfers.

	Both a rack-mount model with rosewood trim and an elegant
	plexiglass enclosed table-top configuration were standard.  Under
	the skin, the basic machine occupies a volume 33 inches high by
	19 inches wide by 22 inches deep.  The two halves of the backplane
	are mounted vertically, like the covers of a book, with the
	spine in back and circuit modules inserted from the two sides.
	Sliding the CPU out of the relay rack or removing the plexiglass
	covers allows the backplane to swung open to access the wires-wrap.

Expandability:  In-cabinet options include the type 182 extended
	arithmetic element (EAE) ($3,500), the type 183 memory extension
	control subsystem ($3000), and the type 189 low performance
	analog to digital converter ($1450).  Prewired backplane slots
	were reserved for all of these, as well as the optional type 129
	data channel multiplexor ($2700).

	Expansion beyond 4K of memory requires rack mounting space (at
	$690 per CAB-8 rack).  Each type 184 memory module adds a 4K
	field of memory ($10,000), seven modules may be added.  The
	rack-mount CPU occupied a large part of one rack, allowing room
	for a single memory expansion module below the CPU; generally,
	a second rack was needed for added peripherals or memory.

	At the end of the production run, some PDP-8 systems were sold
	with PDP-8/I memory, allowing room for an additional 4K without
	need for an expansion chassis.  These nonstandard machines were
	very difficult to maintain!

Peripherals:  At the time of introduction, the following negibus
	peripherals were offered.

	-- Type 750 high speed paper tape reader and control ($3500).
	-- Type 75A high speed paper tape punch and control ($4000).
	-- Type 138 analog to digital converter ($4500).
	-- Type 139 analog multiplexor ($3300).
	-- Type 30N precision CRT display ($13,400).
	-- Type 34B oscilloscope display ($3600).
	-- Type 370 high speed light pen ($1625)
	-- Type 350 incremental (CalComp) plotter and control ($8,900 up).
	-- Type 451 card reader and control ($14,900).
	-- Type 451B fast card reader and control ($25,600).
	-- Type 450 card punch control for IBM Type 523 punch.
	-- Type 64 (later 645) Mohawk line printer and control ($28,900).
	-- Type 250 (RM08) serial magnetic drum (256K words for $43,600).
	-- Type 552 DECtape control (for type 555 DECtape drives, $9500).
	-- Type 555 dual DECtape transport, $7400).
	-- Type 57A magnetic tape control with IBM type 729 drive ($15,200).
	-- Type 580 magnetic tape system with one transport ($19,700).

	By 1966, the following peripherals had been added to the line:

	-- Type AA01A three-channel digital to analog converter.
	-- Type CR01C card reader control.
	-- Type TC01 DECtape control for up to 8 TU55 transports.
	-- Type 251 drum (8-256 tracks, 8 sectors/track, 128 words/sector).
	-- Type 645 line printer control.
	-- Type 680 data communications system (allows 64 teletypes).

	By 1967, the following peripherals had been added to the line:

	-- Type AF01 analog to digital converter and multiplexor.
	-- Type AX08 parallel digital input port.
	-- Type 338 Programmed Buffered Display (vector graphics).

	By 1968, the following new peripheral had been added:

	-- Type DF32 fixed head disk system (32K to 256K words).
	-- Type BE01 OEM version of the TC01 (no blinking lights).
	-- Type BE03 dual TU55 drive for the TC01 or BE01.

	Finally, as DEC abandoned the negibus, they introduced the
	DW08B negibus to posibus converter so newer posibus
	peripherals could be used on older negibus machines, and the
	DW08A posibus to negibus converter to allow use of old
	peripherals on new machines.

Survival:  Many classic PDP-8 systems survive to this day in working
	condition.

------------------------------

Subject: What is a LINC-8?

Date of introduction:  1966 (during or before March).
Date of withdrawal:    1969
Total production run:  142.
Price: $38,500

Technology:  DEC Flip Chip modules, as in the PDP-8, with a LINC CPU
	partially reimplemented in Flip Chips and partially emulated
	with PDP-8 instructions.  (The original LINC was built from
	the same System Modules used in the PDP-5.)

Compatability:  The PDP-8 part of the machine was identical to the PDP-8.

Reason for withdrawal:  The PDP-12 accomplished the same goals at a lower
	cost.

Standard configuration:  The combined PDP-8/LINC CPU, plus 4K of memory
	was central to the system.  The set of peripherals bundled with
	the machine was impressive:

	-- An ASR 33 Teletype modified for the LINC character set.
	-- Two LINCtape drives.
	-- 8 analog to digital converter channels with knob inputs.
	-- Another 8 ADC channels with jack inputs.
	-- 6 programmable relay outputs, good up to 60 Hz.
	-- 1 Tektronix 560 oscilliscope, somewhat modified.

	The X and Y axis control for the scope came from DACs attached
	to the LINC's AC and MB registers, respectively.

Expandability:

	In addition to standard PDP-8 peripherals, up to 3 additional
	pairs of LINCtape drives could be added, for a total of 8 drives.
	The design of the type 555 dual DECtape transport was based on
	that of the LINCtape drive.

	Up to 2 additional ranks of 8 ADC channels could be added.

	Remote oscilliscope could be added.

Survival:  A few LINC-8 systems are in operable condition today.

------------------------------

Subject: What is a PDP-8/S?

Date of introduction:  1966 (Unveiled, Aug 23, WESCON, Los Angeles).
Date of withdrawal:    1970.
Total production run:  1024, or over 1500
	The first figure is from Computers and Automation, based on figures
	released by the manufacturer.  The second figure is based on memory
	of the first-year production run.  We need to look at the serial
	numbers on surviving machines to pin this down!
Price: $10,000

Technology:  DEC Flip Chip modules and core memory, as in the PDP-8.
	Unlike the PDP-8, the PDP-8/S memory module was mounted between
	a pair of quad-height single-width boards that plugged into the
	standard flip-chip sockets (this was sold separately as the H201
	core memory unit, at $2000 for 4K by 13 bits).  It is noteworthy
	that the prototype machine was built using Digital Logic Laboratory
	H901 plugboards and patchcords, based entirely on off-the-shelf
	modules.  Another new feature of the PDP-8 was its use of a single
	internal bus within the machine for all register transfers.  This
	was, of course, bit serial, but the idea formed the basis for
	the DEC UNIBUS and OMNIBUS and essentially all later bus-oriented
	CPU designs.

Reason for introduction:  This machine was developed as a successful
	exercise in minimizing the cost of the machine, in response to
	a complaint by Ken Olson that the company hadn't gotten the
	price of the PDP-8 down any further, and the vision that someday,
	people ought to be able to buy a desktop PDP-8 for under $10,000.
	The result was the least expensive general purpose computer ever
	made with second generation (discrete transistor) technology,
	and it was one of the smallest such machines to be mass produced
	(a number of smaller machines were made for aerospace
	applications).  It was also incredibly slow, with a 36
	microsecond add time, and some instructions taking as much as 78
	microseconds, even though the internal clock ran faster than
	that of the original PDP-8!  By 1967, DEC took the then unusual
	step of offering this machine for off the shelf delivery, with
	one machine stocked in each field office available for retail
	sale.

Reason for withdrawal:  The PDP-8/L vastly outperformed the PDP-8/S, and
	and it did so at a lower price.

Compatability:  The core of the PDP-8 instruction set is present, but
	there are a sufficient number of incompatabilities that, as with
	the PDP-5, many otherwise portable "family of 8" programs will
	not run on the PDP-8/S.  Perhaps the worst incompatability is
	that the Group 1 OPR instruction CMA cannot be combined with any
	of the rotate instructions; as with the PDP-8, IAC also cannot
	be combined with rotate.

Standard configuration:  CPU with 4K of memory, plus PT08 110 baud current
	loop teletype interface and teletype.  Both a rack-mount and
	table-top versions were sold (both 9" high by 19" wide by 20"?
	deep).  The rack mount version included slides so it could be
	pulled out for maintenance.

Expandability:  The CPU supported the standard PDP-8 negibus, but I/O
	bandwidth was 1/5 that of the PDP-8.  Thus, most, but not all
	PDP-8 peripherals could be used.  A few DEC peripherals such as
	the DF32 came with special options such as interleaving to slow
	them down for compatability with the PDP-8/S.  The speed problems
	were such that there was never any way to attach DECtape to this
	machine.

Survival:  Because they were so slow, PDP-8/S systems were quickly
	discarded as newer machines became available for comparable prices;
	thus, they are less common today than the Classic PDP-8, even
	though comparable numbers were made.  A few survive in working
	condition.

------------------------------

Subject: What is a PDP-8/I?

Date of introduction:  1968 (Announced before December '67)
Date of withdrawal:    1971.
Total production run:  3698.

Technology:  DEC M-series logic modules, called M-series flip-chips
	as the term flip-chip was applied to the module format instead
	of to DEC's hybrid integrated circuits.  M-series modules used
	TTL chips, with a +5 volt supply, packaged on the same board
	format used with the original flip-chips, but with double-sided
	card-edge connectors (36 contacts instead of 18).  Modules were
	limited to typically 4 SSI ICs each.  The M113, a typical
	M-series module, had 10 2-input nand gates and cost $23 in 1967
	(the price fell to $18 in 1970).  Wire-wrapped backplanes used
	30-gauge wire.

	The PDP-8/I, as originally sold, supported the then-standard
	PDP-8 negibus.  4K words of core were packaged in a 1 inch thick
	module made of 5 rigidly connected 5 by 5 inch two-sided printed
	circuit boards.  Connectors and support electronics occupied an
	additional 32 backplane slots.

	Nominally, the core memory (which, curiously, used a negative
	logic interface!) was supposed to run at a 1.5 microsecond cycle
	time, but many early PDP-8/I systems were delivered running at a
	slower rate because of memory quality problems.  DEC went through
	many vendors in the search for good memory!  The memory interface
	was asynchronous, allowing the CPU to delay for slow memory.  DEC
	continued to make the classic PDP-8 until the problems with
	memory speed were solved.

Reason for introduction:  This machine was developed in response to the
	introduction of DIP component packaging of TTL integrated
	circuits.  This allowed a machine of about the same performance
	as the original PDP-8 to fit in about half the volume and sell
	for a lower price.

Reason for withdrawal:  The PDP-8/E made slight performance improvements
	while undercutting the price of the PDP-8/I.

Compatability:  The core of the PDP-8 instruction set is present, and
	unlike the original PDP-8, IAC can be combined with rotate in a
	single microcoded Group 1 OPR instruction.  Combined RAR and RAL
	or RTR and RTL produce the logical and of the expected results
	from each of the combined shifts.

	If the extended arithmetic element is present, the SWP (exchange
	AC and MQ) instruction works, but this was not documented.

	On large memory configurations, memory fetches from a nonexistant
	memory field take about 30 microseconds (waiting for a bus
	timeout) and then they return either 0000 or 7777 depending on
	the memory configuration and the field that was addressed.

	A front panel bug prevented continue after load-address without
	first clearing the machine.

Standard configuration:  CPU with 4K of memory, plus 110 baud current
	loop teletype interface.  Pedestal, table-top and rack-mount
	versions were made.  The pedestal mounted version was futuristic
	looking; the table-top version split the pedistal, with the CPU
        on the table and the power supply (the base of the pedistal) on
	the floor beside the table.  The standard rack-mounted version
	had the power supply bolted to the right side of the rack while
	the CPU, mounted on slides, slid out of the left side of the rack.

Expandability: 4K of memory could be added internally, and additional
	memory could be added externally using a rack-mounted MM8I memory
	expansion module for each 4K or 8K addition over 8K.

	The backplane of the PDP-8/I was prewired to hold a Calcomp
	plotter interface, with the adjacent backplane slot reserved
	for the cable connection to the plotter.  There may be other
	built-in options.

	Initially, the CPU was sold with bus drivers for the PDP-8
	negibus, allowing this machine to support all older DEC
	peripherals, but later machines were sold with posibus interfaces,
	and many older machines were converted in the field.

	A posibus to negibus converter, the DW08A, allowed use of all
	older PDP-8 peripherals, with small modifications.  The change
	from negibus to posibus during the period of PDP-8/I production
	leads to confusion because surviving CPUs and peripherals may
	have any of three I/O bus configurations: Negibus, early posibus,
	or final posibus.  The early posibus used the same connectors
	and cables as the negibus, with only 9 conductors per connector,
	while the final posibus used both sides of the connector paddles
	for 18 bus lines per connector.  Y-shaped cables for converting
	from one physical bus layout to the other were available.  To
	add to this confusion, some negibus PDP-8/I systems were rewired
	to use 18 conductor posibus cables with negative logic!

	Eventually, an add-on box was sold that allowed PDP-8/E (OMNIBUS)
	memory to be added to a PDP-8/I.  Additionally, Fabritek sold a
	24K memory box for the 8/I and PDP-12.

Survival:  Many PDP-8/I systems are in operating condition, some still
	performing in their original applications!

------------------------------

Subject: What is a PDP-8/L?

Date of introduction:  1968 (Announced before August '68)
Date of withdrawal:    1971.
Total production run:  3902.
Price: $8,500

Technology:  DEC M-series flip Chip modules, as in the PDP-8/I, with the
	same core memory as the 8/I, but with a memory cycle cycle of 1.6
	microseconds to avoid the speed problems that plagued early -8/I
	systems.

	The positive I/O bus, or posibus, was a 100 ohm bus clamped
	between 0 and 3 volts with TTL drivers and receivers.  This was
	packaged with 18 signal lines per 2-sided interconnect cable,
	using double-sided shielded mylar ribbon cable in most cases.
	Electrically, coaxial cable could be used, but the slots in the
	CPU box were too small for this.

Reason for introduction:  This machine was developed as a moderately
	successful exercise using M-series logic to produce a lower cost
	but moderately fast machine.  The idea was to cut costs by
	limiting provisions for expansion.

Reason for withdrawal:  The PDP-8/E made performance improvements while
	slightly undercutting the price of the PDP-8/L.

Compatability:  The core of the PDP-8 instruction set is present, but
	all Group 3 OPR instructions are no-ops, even the Group 3 version
	of the CLA instruction.  This is because there was no provision
	made for adding an EAE to this machine.  Microcoding RAR and RAL
	together works as in the PDP-8/I.  Finally, a new front panel
	feature was added, the protect switch.  When thrown, this makes
	the last page of the last field of memory read-only (to protect
	your bootstrap code).

	The instruction to change the data field on an 8/L becomes a
	no-op when the destination data field is non-existant; on all
	other machines, attempts to address non-existant fields are
	possible.  One option for expanding the 8/L was to add a box that
	allowed 8/E memory modules to be added to the 8/L; when this
	was done, access to nonexistant data fields becomes possible and
	always returns 0000 on read.

Standard configuration:  A CPU with 4K of memory, plus 110 baud current
	loop teletype interface was standard.  Both rack-mount and
	table-top versions were sold (both 9" high by 19" wide by 21"
	deep).  The backplane was on top, with modules plugged in from
	the bottom.  The rack-mount version could be slid out for
	maintenance.

Expandability:  The CPU supported a new bus standard, the PDP-8 posibus.
	There is little space for in-box peripherals, but an expander
	box with the same volume as the CPU was available, the BA08A;
	this was prewired to hold an additional 4K of memory and to
	support in-box peripheral interfaces for such devices as a
	Calcomp plotter interface, a card-reader interface, a 4 line
	asynch terminal interface, a real-time clock, and more.

	DEC eventually offered the BM12L, an 8K expansion box that is
	essentially the same as the MM8I, but using positive logic and
	thus incompatable with the -8/I and -12.  This allowed a total
	memory of 12K on a PDP-8/L.  This contains precisely the modules
	needed to upgrade a 4K PDP-8/I or PDP-12 to an 8K machine, or to
	populate an MM8I box to add 8K of additional memory to an 8/I or
	PDP-12.

	Finally, DEC eventually offered a box allowing PDP-8/E (OMNIBUS)
	memory to be used with the PDP-8/L.  PDP-8/L configurations with
	over 8K of memory were awkward because the front panel only
	showed one bit of the extended memory address.  As a result,
	extra lights and switches for the additional bits of the memory
	address were mounted on the front of the memory expander boxes
	for the large configurations.

	A variety of posibus peripherals were introduced, most of which
	were built with the option of negibus interface logic (the -P
	and -N suffixes on these new peripherals indicated which was
	which).  Many early PDP-8/L systems were sold with DW08A bus
	level converters to run old negibus peripherals.

	Posibus peripherals introduced after the PDP-8/L (and also used
	with posibus versions of the PDP-8/I) included:

	-- The TC08 DECtape controller (for 8 TU55 or 4 TU56).
	-- The DF32D fixed head disk controller (a posibus DF32).
	-- The FPP-12 floating point processor.
	-- The TR02 simple magnetic tape control.
	-- The RK08 disk subsystem, 4 disk packs, 831,488 words each.

Survival:  Many PDP-8/L systems are in operating condition, some performing
	their original jobs.

------------------------------

Subject: What is a PDP-12?

Date of introduction:  1969 (February or earlier).
Date of withdrawal:    1973.
Total production run:  3500?
Price: $27,900

Technology:  DEC M-series flip Chip modules, as in the PDP-8/I.

Reason for introduction:  This machine was developed as a follow-up to
	the LINC-8.  Originally it was to be called the LINC-8/I, but
	somehow it got its own number.  In effect, it was a PDP-8/I with
	added logic to allow it to execute the LINC instruction set.

Reason for withdrawal:  The LAB-8/E and the LAB-11 (a PDP-8/E and a
	PDP-11/20 with lab peripherals) eventually proved the equal of
	the PDP-12 in practice, and LINC compatability eventually proved
	to be of insufficient value to keep the machine alive in the
	marketplace.
		
Compatability:  This machine is fully compatable with the PDP-8/I, with
	additional instructions to flip from PDP-8 mode to LINC mode and
	back.  IOT 0 could enable the API, causing trouble with later
	PDP-8 code that assumes IOT 0 is "Clear all flags".  Also, the
	DECtape instruction DTLA (6766) becomes part of a stack-oriented
	extension to the instruction set, PUSHJ, on late model (or field
	updated) machines with the KF12-B backplane.

	The PDP-12 supported trapping of those LINC functions that were
	emulated by software on the LINC-8.  This allowed it to run many
	LINC-8 bootable systems (but not all, due mostly incompatabilities
	in LINKtape support), and it allowed such things as emulation of
	LINKtape instructions for reading and writing disk.

	The TC12F Linktape controller could, with appropriate software,
	read or write DECtape.  This support is unreliable, and is not
	software compatable with the TC01 or TC08 DECtape controller.

Standard configuration:  PDP-8/LINC CPU with 4K of memory, plus 110 baud
	current loop interface, plus output relay registers.  In
	addition, the standard configuration included either two TU55 or
	one TU56 drive, with a PDP-12 only controller allowing it to
	handle LINCtape.  In addition, a 12" scope was always included,
	with a connector that can connect to a second scope.

Expandability:  An analog to digital converter and multiplexor was needed
	to fully support knob-oriented LINC software.

	Other options included:

	-- the KW12 programmable lab clock.

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