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Archive-name: dec-faq/pdp8
Last-modified: Apr 8, 2001

Frequently Asked Questions about the DEC PDP-8 computer.

	By Douglas Jones, jones@cs.uiowa.edu
	(with help from many folks)

Reasonably current versions of this file is available by anonymous FTP from:

	ftp://rtfm.mit.edu/pub/usenet/alt.sys.pdp8
	ftp://ftp.uu.net/usenet/news.answers/dec-faq
	ftp://src.doc.ic.ac.uk:/pub/usenet/news.answers/alt.sys.pdp8

Reasonably current automatic translations of this document to HTML format
for the World Wide Web are available from:

	http://www.faqs.org/faqs/dec-faq/
	http://www.cs.ruu.nl/wais/html/na-dir/dec-faq/.html

An obsolete version of this file is available on the Walnut Creek USENET
FAQ CDROM; another version will be published as part of the FAQbook by
Pamela Greene et al.

This posting conforms to RFC1153 USENET digest format (with exceptions due
to the fact that it is not really a digest).


Contents:

	What is a PDP?
	What is a PDP-8?
	What is the PDP-8 instruction set?
	What does PDP-8 assembly language look like?
	What character sets does the PDP-8 support?
	What different PDP-8 models were made?
	What about the LINC-8 and PDP-12?
	Where can I get a PDP-8 today?
	Where can I get PDP-8 documentation?
	What operating systems were written for the PDP-8?
	What programming languages were supported on the PDP-8?
	Where can I get PDP-8 software?
	Where can I get additional information?
	What use is a PDP-8 today?
	Who's Who?

----------------------------------------------------------------------

Subject: What is a PDP?

In 1957, Ken Olson and Harlan Anderson founded Digital Equipment
Corporation (DEC), capitalized at $100,000, and 70% owned by American
Research and Development Corporation.  Olson and Anderson had designed
major parts of the AN/FSQ-7, the TX-0 and the TX-2 computers at
Lincoln Labs.  They wanted to call their company Digital Computer
Corporation, but the venture capitalists insisted that they avoid the
term Computer and hold off on building computers.

With facilities in an old woolen mill in Maynard Massachusetts, DEC's
first product was a line of transistorized digital "systems modules"
based on the modules used in building TX-2 at Lincoln Labs; these
were plug-in circuit boards with a few logic gates per board.  Starting
in 1960, DEC finally began to sell computers (the formal acceptance of
the first PDP-1 by BBN is reported in Computers and Automation, April
1961, page 8B).  Soon after this, there were enough users that DECUS,
the Digital Equipment Computer User's Society was founded.

DEC's first computer, the PDP-1, sold for only $120,000 at a time when
other computers sold for over $1,000,000.  (A good photo of a PDP-1 is
printed in Computers and Automation, Dec. 1961, page 27).  DEC quoted
prices as low as $85,000 for minimal models.  The venture capitalist's
insistance on avoiding the term computer was based on the stereotype
that computers were big and expensive, needing a computer center and a
large staff; by using the term Programmable Data Processor, or PDP, DEC
avoided this stereotype.  For over a decade, all digital computers sold
by DEC were called PDPs.  (In early DEC documentation, the plural form
"PDPs" is used as a generic term for all DEC computers.)

In the early 1960's, DEC was the only manufacturer of large computers
without a leasing plan.  IBM, Burroughs, CDC and other computer
manufacturers leased most of their machines, and many machines were
never offered for outright sale.  DEC's cash sales approach led to the
growth of third party computer leasing companies such as DELOS, a
spinoff of BB&N.

DEC built a number of different computers under the PDP label, with a
huge range of price and performance.  The largest of these are fully
worthy of large computer centers with big support staffs.  Some early
DEC computers were not really built by DEC.  With the PDP-3 and LINC,
for example, customers built the machines using DEC parts and
facilities.  Here is the list of PDP computers:

    MODEL  DATE  PRICE    BITS NUMBER COMMENTS
    =====  ====  ======== ==== ====== ========
    PDP-1  1960  $120,000 18       50 DEC's first computer
    PDP-2            NA   24        - Never built?  Prototype only?
    PDP-3            NA   36          One built by a customer*, not by DEC.
    PDP-4  1962   $60,000 18       45 Predecessor of the PDP-7.
    PDP-5  1963   $27,000 12    1,000 The ancestor of the PDP-8.
    PDP-6  1964  $300,000 36       23 A big computer; 23 built, most for MIT.
    PDP-7  1965   $72,000 18      120 Widely used for real-time control.
    PDP-8  1965   $18,500 12  ~50,000 The smallest and least expensive PDP.
    PDP-9  1966   $35,000 18      445 An upgrade of the PDP-7.
    PDP-10 1967  $110,000 36   **~700 A PDP-6 followup, great for timesharing.
    PDP-11 1970   $10,800 16 >600,000 DEC's first and only 16 bit computer.
    PDP-12 1969   $27,900 12      725 A PDP-8 relative.
    PDP-13           NA             - Bad luck, there was no such machine.
    PDP-14                        *** A ROM-based programmable controller.
    PDP-15 1970   $16,500 18      790 A TTL upgrade of the PDP-9.
    PDP-16 1972      NA   8/16      ? A register-transfer module system.

*  Scientific Engineering Institute of Waltham MA.  SEI was aledgedly
     founded in 1956 by the CIA to study the effects of microwaves (radar)
     on the human brain.  If so, the PDP-3 may have been used as an
     instrumentation computer.  More info on the CIA connection and the
     use of the PDP-3 would be nice!
** Includes DECsystem 20.

Corrections and additions to this list are welcome!  The prices given
are for minimal systems in the year the machine was first introduced.
Most of the production run numbers come from "Computer Engineering" by
Bell, Mudge and McNamara, 1978, or from Computers and Automation's
computer census figures published regularly throughout the 1960's.
The bits column in the table indicates the word size.  Note that the
DEC PDP-10 became the DECSYSTEM-20 as a result of marketing
considerations, and DEC's VAX series of machines began as the Virtual
Address eXtension of the never-produced PDP-11/78.

It is worth mentioning that it is widely (but somewhat incorrectly)
accepted that the Data General Nova (see photo, Computers and
Automation, Nov. 1968, page 48) grew out of the PDP-X, a 16-bit
multi-register version of the PDP-8 designed by Edson DeCastro, Henry
Burkhardt and Dick Soggee.  (DeCastro was one of DEC's key design
engineers; his name appears on many of the blueprints for machines
from the PDP-5 up through the PDP-8/L).

A prototype PDP-X was built at DEC; this and a competing 16-bit design
were apparently submitted to Harold McFarland at Carnegie-Mellon
University for evaluation; McFarland (and perhaps Gordon Bell, who was
at C-MU at the time) evaluated the competing designs and rejected both
in favor of what we now know as the PDP-11.  (I was at Carnegie-Mellon
at the time, and McFarland gave a guest lecture in a class I attended
telling part of this story.)  Some speculate, incorrectly, that Bell
rejected the Nova design because the competing proposal used the
register-transfer notation he had introduced in "Bell and Newell,
Computer Structures -- Readings and Examples".  An alternate and equally
unfounded story is that the reason DEC never produced a PDP-13 was
because the number 13 had been assigned to what became the Nova.

In any case, when DeCastro, Burkhardt and Soggee founded Data General,
Ken Olson at DEC was very angry, claiming for a long time that the
Nova design was stolen.  Gordon Bell and others concluded that the
Nova design was sufficiently original that a lawsuit was unwarranted,
but the feud between DeCastro and Olson lasted until after Ken Olson
left DEC.  It is more correct to say that the Nova is a reaction to the
PDP-X than to say that it is based on the PDP-X.  I am indebted to
Jim Campbell, retired VP at Data General, for some of the details of
this story.

Today, all of the PDP machines are in DEC's corporate past, except the
PDP-11 family, which survives as a line of microcomputers; DEC has
promised to discontinue PDP-11 sales on Sept. 30, 1996.  Occasionally,
some lab has built a machine out of DEC hardware and called it a PDP
with a new number.  For example, the Australian Atomic Energy Commission
once upgraded a PDP-7 by adding a PDP-15 on the side; they called the
result a PDP-22.  There is also a story about the PDP-2 1/2, built by
Ed Rawson of the American Science Institute out of surplus modules that
were originally used in the prototype PDP-2.

In 1998, Compaq purchased DEC, and it is unclear how long DEC will retain
any semblance of its original identity as a division of a larger company.

------------------------------

Subject: What is a PDP-8?

The PDP-8 family of minicomputers were built by Digital Equipment
Corporation between 1965 and 1990, although it is worth noting that the
term minicomputer first came into prominence after the machine was
introduced.  The first use of the term appears to have been made by
the head of DEC's operations in England, John Leng.  He sent back a
sales report that started: "Here is the latest minicomputer activity
in the land of miniskirts as I drive around in my [Austin] Mini Minor."
The term quickly became part of DEC's internal jargon and spread from
there; the first computer explicitly sold as a minicomputer, though,
was made by by Interdata (See the Interdata ad in Computers and
Automation, May 1968, page 10).

The PDP-8 was largely upward compatible with the PDP-5, a machine that
was unveiled on August 11, 1963 at WESCON, and the inspiration for that
machine came from two earlier machines, the LINC and the CDC 160.  All
of these machines were characterized by a 12 bit word with little or no
hardware byte structure, typically 4K words of memory, and simple but
powerful instruction sets.

Although some people consider the CDC 160 the first minicomputer, the
PDP-8 was the definitive minicomputer.  By late 1973, the PDP-8 family
was the best selling computer in the world, and it is likely that it was
only displaced from this honor by the Apple II (which was displaced by
the IBM PC).  Most models of the PDP-8 set new records as the least
expensive computer on the market at the time of their introduction.
The PDP-8 has been described as the model-T of the computer industry
because it was the first computer to be mass produced at a cost that
just about anyone could afford.

C. Gordon Bell has said that the basic idea of the PDP-8 was not really
original with him.  He gives credit to Seymour Cray (of CDC and later
Cray) for the idea of a single-accumulator 12 bit minicomputer.  Cray's
CDC 160 family (see CACM, march 1961, photo on page 244, text on page
246) was such a machine, and in addition to the hundreds of CDC 160
systems sold as stand-alone machines, a derivative 12 bit architecture
was used for the I/O processors on Cray's first great supercomputer,
the CDC 6600.

Note that Cray's 12 bit machines had 6 basic addressing modes with
variable length instruction words and other features that were far from
the simple elegance of the PDP-8.  Despite its many modes, the CDC 160
architecture lacked the notion of current page addressing, it had no
unconditional jump instruction, and the I/O instructions all blocked
the CPU until I/O complete.  As a result, the PDP-8 is both far more
flexible and it supports much tighter programming styles.

------------------------------

Subject: What is the PDP-8 instruction set?

The PDP-8 word size is 12 bits, and the basic memory is 4K words.  The
minimal CPU contained the following registers:

	PC - the program counter, 12 bits.
	AC - the accumulator, 12 bits.
	L  - the link, 1 bit, commonly prefixed to AC as .

It is worth noting that many operations such as procedure linkage and
indexing, which are usually thought of as involving registers, are done
with memory on the PDP-8 family.

Instruction words are organized as follows:
	 _ _ _ _ _ _ _ _ _ _ _ _
	|_|_|_|_|_|_|_|_|_|_|_|_|
	|     | | |             |
	|  op |i|z|    addr     |

	op   - the opcode.
	i    - the indirect bit (0 = direct, 1 = indirect).
	z    - the page bit (0 = page zero, 1 = current page).
	addr - the word in page.

The top 5 bits of the 12 bit program counter give the current page, and
memory addressing is also complicated by the fact that absolute memory
locations 8 through 15 are incremented prior to use when used as indirect
addresses.  These locations are called auto-index registers (despite the
fact that they are in memory); they allow the formulation of very tightly
coded array operations.

The basic instructions are:

	000 - AND - and operand with AC.
	001 - TAD - add operand to  (a 13 bit value).
	010 - ISZ - increment operand and skip if result is zero.
	011 - DCA - deposit AC in memory and clear AC.
	100 - JMS - jump to subroutine.
	101 - JMP - jump.
	110 - IOT - input/output transfer.
	111 - OPR - microcoded operations.

The ISZ and other skip instructions conditionally skip the next
instruction in sequence.  The ISZ is commonly used to increment a loop
counter and skip if done, and it is also used as an general increment
instruction, either followed by a no-op or in contexts where it is known
that the result will never be zero.

The JMS instruction stores the return address in relative word zero of
the subroutine, with execution starting with relative word one.
Subroutine return is done with an indirect JMP through the return
address.  Subroutines commonly increment their return addresses to index
through inline parameter lists or to perform conditional skips over
instructions following the call.

The IOT instruction has the following form:
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	|     |           |     |
	|     |   device  | op  |

The IOT instruction specifies one of up to 8 operations on one of 64
devices.  Typically (but not universally), each bit of the op field
evokes an operation, and these can be microcoded in right to left
order.  Prior to the PDP-8/E, there were severe restrictions on the
interpretation of the op field that resulted from the fact that the
operation was delivered as a sequence of IOP pulses, each on a separate
line of the I/O bus.  Each line was typically used to evoke a different
device function, so essentially, the operation 000 was always a no-op
because it evoked no functions, and the code 111 evoked all three
functions in series.

As an example of the use of IOT instructions, consider the console
terminal interface.  On early PDP-8 systems, this was always assumed to
be an ASR 33 teletype, complete with low-speed paper tape reader and
punch.  It was addressed as devices 03 (the keyboard/reader) and 04
(the teleprinter/punch):
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	      |0 0 0 0 1 1|0 0 1  - KSF - keyboard skip if flag
	      |0 0 0 0 1 1|0 1 0  - KCC - keyboard clear flag
	      |0 0 0 0 1 1|1 0 0  - KRS - keyboard read static

The keyboard flag is set by the arrival of a character.  The KCC
instruction clears both the flag and the accumulator.  KRS ors the 8 bit
input data with the low order 8 bits of AC.  The commonly used KRB
instruction is the or of KCC and KRS.  To await one byte of input, use
KSF to poll the flag, then read the byte with KRB.
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	      |0 0 0 1 0 0|0 0 1  - TSF - teleprinter skip if flag
	      |0 0 0 1 0 0|0 1 0  - TCF - teleprinter clear flag
	      |0 0 0 1 0 0|1 0 0  - TPC - teleprinter print static

The teleprinter flag is set by the completion of the TPC operation (as
a result, on startup, many applications output a null in order to get
things going).  TCF clears the flag, and TPC outputs the low order 8
bits of the accumulator.  The commonly used TLS instruction is the or
of TCF and TPC.  To output a character, first use TSF to poll the flag,
then write the character with TLS.

IOT instructions may be used to initiate data break transfers from block
devices such as disk or tape.  The term "data break" was, for years,
DEC's preferred term for cycle-stealing direct-memory-access data
transfers.

Some CPU functions are accessed only by IOT instructions.  For example,
interrupt enable and disable are IOT instructions:
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	      |0 0 0 0 0 0|0 0 1  - ION - interrupts turn on
	      |0 0 0 0 0 0|0 1 0  - IOF - interrupts turn off

An interrupt is requested when any device raised its flag.  The console
master clear switch resets all flags and disables interrupts.  In
effect, an interrupt is a JMS instruction to location zero, with the
side effect of disabling interrupts.  The interrupt service routine
is expected to test the device flags and perform the operations needed
to reset them, and then return using ION immediately before the indirect
return JMP.  The effect of ION is delayed so that interrupts are not
enabled until after the JMP.

The instructions controlling the optional memory management unit are
also IOT instructions.  This unit allows the program to address up to
32K of main memory by adding a 3 bit extension to the memory address.
Two extensions are available, one for instruction fetch and direct
addressing, the other for indirect addressing.

A wide variety of operations are available through the OPR microcoded
instructions:
         _ _ _ _ _ _ _ _ _ _ _ _
Group 1 |1|1|1|0|_|_|_|_|_|_|_|_|
	         1                - CLA - clear AC
	           1              - CLL - clear the L bit
                     1            - CMA - ones complement AC
                       1          - CML - complement L bit
                               1  - IAC - increment 
                         1 0 0    - RAR - rotate  right
                         0 1 0    - RAL - rotate  left
	                 1 0 1    - RTR - rotate  right twice
	                 0 1 1    - RTL - rotate  left twice

In general, the above operations can be combined by oring the bit
patterns for the desired operations into a single instruction.  If none
of the bits are set, the result is the NOP instruction.  When these
operations are combined, they operate top to bottom in the order shown
above.  The exception to this is that IAC cannot be combined with the
rotate operations on some models, and attempts to combine rotate
operations have different effects from one model to another (for example,
on the PDP-8/E, the rotate code 001 means swap 6 bit bytes in the
accumulator, while previous models took this to mean something like
"shift neither left nor right 2 bits").
         _ _ _ _ _ _ _ _ _ _ _ _
Group 2 |1|1|1|1|_|_|_|_|_|_|_|0|
                   1     0        - SMA - skip on AC < 0  \
                     1   0        - SZA - skip on AC = 0   > or group
                       1 0        - SNL - skip on L /= 0  /
                   0 0 0 1        - SKP - skip unconditionally
                   1     1        - SPA - skip on AC >= 0 \
                     1   1        - SNA - skip on AC /= 0  > and group
                       1 1        - SZL - skip on L = 0   /
                 1                - CLA - clear AC
                           1      - OSR - or switches with AC
                             1    - HLT - halt

The above operations may be combined by oring them together, except that
there are two distinct incompatible groups of skip instructions.  When
combined, SMA, SZA and SNL, skip if one or the other of the indicated
conditions are true (logical or), while SPA, SNA and SZL skip if all of
the indicated conditions are true (logical and).  When combined, these
operate top to bottom in the order shown; thus, the accumulator may be
tested and then cleared.  Setting the halt bit in a skip instruction is
a crude but useful way to set a breakpoint for front-panel debugging.
If none of the bits are set, the result is an alternative form of no-op.

A third group of operate microinstructions (with a 1 in the least
significant bit) deals with the optional extended arithmetic element to
allow such things as hardware multiply and divide, 24 bit shift
operations, and normalize.  These operations involve an additional data
register, MQ or multiplier quotient, and a small step count register.
On the PDP-8/E and successors, MQ and the instructions for loading and
storing it were always present, even when the EAE was absent, and the
EAE was extended to provide a useful variety of 24 bit arithmetic
operations.

------------------------------

Subject: What does PDP-8 assembly language look like?

There are many different assemblers for the PDP-8, but most use a
compatible basic syntax; here is an example:

	START,	CLA CLL		/ Clear everything
		TAD	X	/ Load X
		AND I	Y	/ And with the value pointed to by Y
		DCA	X	/ Store in X
		HLT		/ Halt

	X,	1 		/ A variable
	Y,	7 		/ A pointer

Note that labels are terminated by a comma, and comments are separated
from the code by a slash.  There are no fixed fields or column
restrictions.  The "CLA CLL" instruction on the first line is an example
of the microcoding of two of the Group 1 operate instructions.  CLA
alone has the code 7200 (octal), while CLL has the code 7100; combining
these as "CLA CLL" produces 7300.  As a general rule, except when memory
reference instructions are involved, the assembler simply ors together
the values of all blank separated fields between the label and comment.
	
Indirection is indicated by the special symbol I in the operand field,
as in the third line of the example.  The typical PDP-8 assembler has no
explicit notation to distinguish between page zero and current page
addresses.  Instead, the assembler is expected to note the page holding
the operand and automatically generate the appropriate mode.  If the
operand is neither in the current page nor page zero, some assemblers
will raise an error, others will automatically generate an indirect
pointer to the off-page operand; this should be avoided because it only
works for directly addressed off-page operands, and only when the memory
management unit is not being used to address a data field other than the
current instruction field.

Note, in the final two lines of the example, that there is no "define
constant" pseudo-operation.  Instead, where a constant is to be
assembled into memory, the constant takes the place of the op-code field.

The PDP-8 has no immediate addressing mode, but most assemblers provide
a notation to allow the programmer to ignore this lack:

		TAD	(3)	/ add 3, from memory on the current page.
		TAD	[5]	/ add 5, from memory on page zero.
		JMP I	(LAB)	/ jump indirect through the address of LAB.

Assemblers that support this automatically fill the end of each page
with constants defined in this way that have been accumulated during the
assembly of that page.  Note that the variants "(3" and "[5" (with no
closing parentheses) are usually allowed but the use of this sloppy form
is discouraged.  Furthermore, the widely used PAL8 assembler interprets
the unlikely operand "(3)+1" as being the same as "(3+1)".

Arithmetic is allowed in operand fields and constant definitions, with
expressions evaluated in strict left-to-right order, as:

		TAD	X+1	/ add the contents of the location after X.
		TAD	(X-1)	/ add the address of the location before X.

Other operators allowed include and (&), or (!), multiply (^) and divide
(%), as well as a unary sign (+ or -).  Unfortunately, one of the most
widely used assemblers, PAL8, has trouble when unary operators are mixed
with multiplication or division.
	
Generally, only the first 6 characters of identifiers are significant
and numeric constants are evaluated in octal.

Other assembly language features are illustrated below:

	/ Comments may stand on lines by themselves
				/ Blank lines are allowed

		*200		/ Set the assembly origin to 200 (octal)

	NL0002=	CLA CLL CML RTL	/ Define new opcode NL0002.

		NL0002		/ Use new opcode (load 0002 in AC)
		JMP	.-1	/ Jump to the previous instruction

	X1=	10		/ Define X1 (an auto-index register address)
	LETA=	"A		/ Define LETA as 000011000001 (ASCII A)

		TAD I	X1	/ Use autoindex register 1

		IAC; RAL	/ Multiple instructions on one line

		$		/ End of assembly

The assembly file ends with a line containing a $ (dollar sign) not in
a comment field.

The $, * and =  syntax used by most PDP-8 assemblers replaces functions
performed by pseudo-operations on many other assemblers.  In addition,
PAL8, the most widely used PDP-8 assembler supports the following
pseudo-operations:

		DECIMAL		/ Interpret numeric constants in base 10
		OCTAL		/ Interpret numeric constants in base 8
		EJECT		/ Force a page eject in the listing
		XLIST		/ Toggle listing
		XLIST	N	/ Turn on listing if N=0, off if N=1
		PAGE 	 	/ Advance location counter to next page
		PAGE 	N	/ Set location counter start of page N
		FIELD	N	/ Assemble into extended memory field N
		TEXT	"STR"	/ Pack STR into consecutive 6 bit bytes
		ZBLOCK	N	/ Allocate N words, initialized to zero
		IFDEF	S 	/ Assemble C if symbol S is defined
		IFNDEF	S 	/ Assemble C if symbol S is not defined
		IFZERO	E 	/ Assemble C if expression E is zero
		IFNZRO	E 	/ Assemble C if expression E is not zero
		FIXMRI  OP= VAL	/ Define OP as memory reference instruction

Conditonally assembled code must be enclosed in angle brackets.  The
enclosed code may extend over multiple lines and, because different
assemblers treat comments within conditionals differently, the closing
bracket should not be in a comment and any brackets in comments should
be balanced.

------------------------------

Subject: What character sets does the PDP-8 support?

From the beginning, PDP-8 software has generally assumed that textual
I/O would be in 7 bit ASCII.  Most early PDP-8 systems used teletypes
as console terminals; as sold by DEC, these were configured for mark
parity, so most older software assumes 7 bit ASCII, upper case only,
with the 8th bit set to 1.  On output, lines are generally terminated
with both CR and LF; on input, CR is typically (but not always) the
line terminator and LF is typically ignored.  In addition, the tab
character (HT) is generally allowed, but software support output of text
containing tabs varies.

One difficulty with much PDP-8 software is that it bypasses the device
handlers provided by the operating system and goes directly to the
device.  This results in very irregular device support, so that, for
example, control-S and control-Q work to start and stop output under
OS/8, but the OS/8 PAL assembler ignores them when reporting errors.

Most of the better engineered PDP-8 software tends to fold upper and
lower case on input, and it ignores the setting of the 8th bit.  Older
PDP-8 software will generally fail when presented with lower case
textual input (this includes essentially all OS/8 products prior to
OS/278 V1).

Internally, PDP-8 programmers are free to use other character sets, but
the "X notation provided by the assembler encourages use of 7 bit ASCII
with the 8th bit set to 1, and the TEXT pseudo-operation encourages the
6 bit character set called "stripped ASCII".  To map from upper-case-only
ASCII to stripped ASCII, each 8 bit character is anded with octal 77 and
then packed 2 characters per word, left to right.  Many programs use a
semi-standard scheme for packing mixed upper and lower case into 6 bit
TEXT form; this uses ^ to flip from upper to lower case or lower to
upper case, % to encode CR-LF pairs, and @ (octal 00) to mark end of
string.  Note that this scheme makes no provision for encoding the %,
^ and @ characters, nor does it allow control characters other than the
CR-LF pair.

The P?S/8 operating system supports a similar 6 bit text file format,
where upper and lower case are folded together, tabs are stored as _
(underline), end-of-line is represented by 00, padded with any
nonzero filler to a word boundary, and end of file is 0000.

Files under the widely used OS/8 system consist of sequences of 256 word
blocks.  When used for text, each block holds 384 bytes, packed 3 bytes
per pair of words as follows:

		aaaaaaaa		ccccaaaaaaaa
		bbbbbbbb		CCCCbbbbbbbb
		ccccCCCC

Control Z is used as an end of file marker.  Because most of the PDP-8
system software was originally developed for paper tape, binary object
code is typically stored in paper-tape image form using the above packing
scheme.

------------------------------

Subject: What different PDP-8 models were made?

The total sales figure for the PDP-8 family is estimated at over 300,000
machines.  Over 7000 of these were sold prior to 1970, and 30,000 were
sold by 1976.  During the PDP-8 production run, a number of models were
made, as listed in the following table.  Of these, the PDP-8/E is generally
considered to be the definitive machine.  If the PDP-8 is considered to
be the Model T of the computer industry, perhaps the PDP-8/E should be
considered to be the industry's Model A.

    MODEL	DATES	SALES   COST	TECHNOLOGY	REMARKS

    PDP-5	63-67	 116		Transistor
    PDP-8	65-69 	1450	$18,500	Transistor
    LINC-8	66-69	 142	$38,500	Transistor
    PDP-8/S	66-70	1024	$10,000	Transistor	Very slow
    PDP-8/I	68-71 	3698	$12,800	TTL
    PDP-8/L	68-71 	3902	 $8,500	TTL		Scaled down 8/I
    PDP-12	69-73?	3500?	$27,900	TTL		Followup to LINC-8
    PDP-8/E	70-78	>10K?	 $6,500	TTL MSI	Omnibus
    PDP-8/F	72-78?	>10K?	<$5K	TTL MSI Omnibus	Based on 8/E CPU
    PDP-8/M	72-78?	>10K?	<$5K	TTL MSI Omnibus	OEM version of 8/F
    PDP-8/A	75-84?	>10K?	 $1,317	TTL LSI Omnibus	New CPU or 8/E CPU
    VT78	78-80		 $7,995	Intersil 6100	Workstation
    DECmate I	80-84			Harris 6120	Workstation
    DECmate II	82-86		 $1,435	Harris 6120	Workstation
    DECmate III	84-90		 $2,695	Harris 6120	Workstation
    DECmate III+85-90			Harris 6120	Workstation

Additional information is available in part two of this FAQ, where all
known models of the PDP-8, along with variants, alternate marketing
names, and other peculiarities are given.

The last years of the PDP-8 family were dominated by the PDP-8 compatible
microprocessor based VT78 and DECmate workstations.  The Intersil 6100,
also known as the CMOS-8 chip, was developed in 1976; GE later acquired
Intersil.  DEC also used the followup Harris 6120 microprocessors
(Introduced 1981) in many peripheral controllers for the PDP-11 and
PDP-15 as well as in the DECmate series of systems.  While all of the
earlier PDP-8 systems were open architecture systems, the DECmates had
closed architectures with an integrated console terminals and limited
peripheral options.  It is interesting to note that the Harris 6120 was
a 10Mhz chip and some chips could be clocked at 15Mhz; furthermore, the
6120 was essentially based on gate array technology.

The following PDP-8 compatible or semi-compatible machines were made and

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