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FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)

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   This is the FAQ (Frequently Asked Questions) list for the newsgroup
   comp.lang.verilog. It is an attempt to gather in one place the answers
   to common questions and to maintain an updated list of publications,
   services, and products. Please read this document before posting.
   This article is posted bi-weekly. It is also available from the
   archive for this group.
   If you haven't already done so, reading the posts on
   news.announce.newusers titled "A Primer on How Work With the Usenet
   Community", "Answers to Frequently Asked Questions about Usenet" and
   "Hints on writing style for Usenet" would be a good idea. They are "a
   guide to using it [Usenet] politely, effectively and efficiently."
   Your comments, additions, and corrections to this list are welcome:
   Please send them to Steve Phillips .
P01: Table of Contents

          + new
          - deleted
          ! changed
       P01: Table of Contents
       P02: Viewing this article
       P03: ! Where to get the most recent version of this FAQ
       P04: How does FTP work?
       I01: What is Verilog?
       I02: Who's bright idea was this? (A short history)
       I03: What is comp.lang.verilog?
       I04: Is there an archive for this group?
       I05: Is the archive available on the Web, through clients like
       Mosaic and Lynx?
    General Topics
       G01: Is there a verilog.el for GNU emacs?
       G02: What is PLI?
       G03: Is there a version that runs on a IBM PC clone?
       G04: What is the best PC clone simulator?
       G05: What is the best workstation simulator?
       G06: Is there a vgrind def file?
       G07: Is there a free verilog parser available?
       G08: Is there a free Verilog simulator?
       G09: Is there a Verilog test suite?
       G10: Where can I find a free Verilog quick reference card?
       G11: Are there related Web sites? 
       A01: Verilog vendors and products
       A02: Books and Reference material on Verilog
Subject: P02: Viewing this article

   This article is now written as an HTML document. The plain text
   version is generated by dump the HTML with lynx. This means that it is
   no longer in digest format. This makes it a little less useable as a
   plain text document, but a lot nicer as a web ducument.
   To skip to a particular question numbered xxx, use "/xxx" with most
   pagers. In GNU Emacs type "M-C-s xxx", (or C-r to search backwards),
   followed by ESC to end the search.
Subject: P03: Where to get the most recent version of this FAQ

   This FAQ is now available from the usual places:
   o RTFM FAQ archives
   o Ohio State Usenet FAQ archives
   It is also posted frequently to comp.lang.verilog, and is available
   from the archive site (see I04: Is there an archive for this group? ).
Subject: P04: How does FTP work?

   FTP is a way of copying files between networked computers. If you need
   help in using or getting started with FTP, send e-mail to
   send /pub/usenet-by-group/news.answers/ftp-list/faq
   in the body.
Subject: I01: What is Verilog?

   Verilog HDL is a hardware description language used to design and
   document electronic systems. Verilog HDL allows designers to design at
   various levels of abstraction. It is the most widely used HDL with a
   user community of more than 15000 active designers.
Subject: I02: Who's bright idea was this? (A short history)

   [contributed by Asad Khan  ]
   Verilog HDL originated circa 1983 at Gateway Design Automation, which
   was then located in Acton, MA. The company was privately held at that
   time by Dr. Prabhakar Goel, the inventor of the PODEM test generation
   algorithm. Verilog HDL was designed by Phil Moorby, who was later to
   become the Chief Designer for Verilog-XL and the first Corporate
   Fellow at Cadence Design Systems.
   Moorby built a simulator around Verilog-XL in 1984-85, and then went
   on to make his second major contribution at GDA, viz. the XL algorithm
   for every fast gate-level simulation, which was first productized in
   Gateway Design Automation grew rapidly with the success of Verilog-XL
   and was finally acquired by Cadence Design Systems, San Jose, CA in
   1989. Up till this time, Verilog HDL was still a proprietary language,
   being the property of Cadence Design Systems.
   Cadence Design Systems decided to open the language to the public in
   1990, and thus OVI was born.
   [contributed by John Sanguinetti  ]
   When OVI was formed in 1991, a number of small companies began working
   on Verilog simulators. The first of these came to market in 1992, and
   now there are mature Verilog simulators available from several souces.
   As a result, the Verilog market has grown substantially. The market
   for Verilog-related tools in 1994 was well over $75m, making it the
   most commercially significant hardware description language on the
   Verilog is now in the process of being standardized by the IEEE. There
   is an IEEE working group established under the Design Automation
   Sub-Committee which was established in 1993 to produce the IEEE
   Verilog standard 1364. This working group is currently active and
   expects to produce a draft standard for balloting sometime in 1995.
Subject: I03: What is comp.lang.verilog?

   [extracted from]
   comp.lang.verilog is an unmoderated newsgroup which passed its vote
   for creation by 332:9 as reported in news.announce.newgroups on 12 Dec
   For your newsgroups file:
   comp.lang.verilog Discussing Verilog and PLI.
   The charter, culled from the call for votes:
   The USENET group is intended at providing a forum for the discussion
   of topics specific to Verilog, PLI (programming language interface),
   SDF (Standard delay file format), Synthesis guidelines, compliance and
   Verilog modeling. It will also provide users with an ability to share
   Verilog/PLI utilities. Users can also use the forum to discuss any
   Verilog related issues proposed by Open Verilog International and its
   organizational and technical committees.
Subject: I04: Is there an archive for this group?

   Yes. Out of the goodness of our hearts, we here at Cray Research
   provide an anonymous ftp archive for the postings to comp.lang.verilog
   and related files and information. This archive is read only; Cray
   does not allow non-employees to write into its file systems. If you
   have something to contribute, send it to me ( and I will
   upload it.
   In addition, the University of Windsor maintains an archive of
   postings to several of the CAD related newsgroups. One of these is
Subject: I05: Is the archive available on the Web, through clients like Mosaic
and Lynx?

   Cray also provides space on the Cray Research Web Server for the
   Comp.lang.verilog home page:
   In fact, this FAQ is actually a html document. The text version is
   created by dumping the html version with lynx. The html version can be
   accessed from the archive home page, or directly at:
Subject: G01: Is there a verilog.el for GNU emacs?

   The archives contain no less than three verilog modes for emacs:
       Rick Eversole at Cadence maintains a verilog mode and occasionally
       posts it to comp.lang.verilog. At this time it supports only FSF
       18.xx and Epoch. FSF 19.xx and Lucid Emacs (lemacs) are not
       supported. It is available at the archive site, or send email to to request a copy if you have missed the
       posting and can not get it from the archive of comp.lang.verilog.
       This one was written by Michael McNamara ( I
       grabbed this off the net last fall.
       This one was written by Phil Welling ( and
       was also grabbed from a posting.
   In addition, Cadence is now shipping an LSE (Language Sensitive
   Editor) that appears to consist of Lucid Emacs with a set of elisp
   files to implement the verilog mode.
Subject: G02: What is PLI?

   PLI stands for Programming Language Interface. The PLI consists of an
   interface mechanism, a set of routines to interact with the simulation
   environment, and a set of routines to access the Verilog internal data
   structures. These allow user supplied C code to interact dynamically
   with the simulation and data structures.
Subject: G03: Is there a version that runs on a IBM PC clone?

   See section A01: Verilog vendors and products
Subject: G04: What is the best PC clone simulator?

   The answer, of coarse, depends on what you are looking for. However,
   Yatin Trivedi has made available a summary of an evaluation of the PC
   clone verilog simulators currently available:

        Here is the summary of the PC_based Verilog simulator
        Product Evaluation results. These results and a discussion
        of the evaluation appeared in ASIC & EDA Magazine, (Product
        Evaluation, PC based Verilog Simulators, April 1994,
        pages 12-36), and Electronic Engineering Times (Verilog
        Simulators get benchmark grilling, April 25, Page 114).

        A detailed report of raw performance numbers and the
        scoring schemes are available in a report from Seva
        Technologies (510-249-9085 or 408-223-1231).

        The evaluation was ranked using SEVA Evaluation Index (SEI)
        derived by talking with more than 50 different users.

        SEI Criteria    Weight
        ============    ======

        Performance     40%
        Debugging       20%
        Language        15%
        Design Envr     10%
        Tech Doc &       5%
        PLI Implem       4%
        Specify Block    4%
        Installation     2%
         & Licensing

        Performance was measured in terms of compile time, run time,
        and memory used.
        There were 9 different models run with small, medium, and
        large number of vectors.

        The 9 models were divided in small, medium, and large models
        at gate level, RTL, and mixed.
        More than 125 compliance test cases were run.

        Run time was at least 3 minutes for the fastest simulator
        to avoid any measurement inaccuracies.
        Simulator/Vendor        SEI Score       SEI/$1,000
        ================        =========       ==========

        VeriBest/Intergraph     73.9             4.93
        FinSim/Fintronic        63.7             9.10
        SILOS III/Simucad       62.3            20.77
        Baseline/Frontline      61.9            10.32
        Veriwell/Wellspring     29.7            29.85
        Viper/InterHDL          25.9            26.03

        Seva EValuation Academy Awards 1994 (SEVA Awards) goes to
        (drum rolls, please...)

        Serious User's Simulators       ==>     VeriBest, Silos III, Baseline
        Best Price/Performance          ==>     Silos III, Baseline
        Cost-conscious User's choice    ==>     Veriwell, Viper
        Best Performance                ==>     VeriBest, Silos III
        Most Compliant                  ==>     Baseline, VeriBest
        Best Documentation              ==>     Baseline, Silos III
        Macintosh Compatibility         ==>     Veriwell

        Note: VeriBest uses Finsim as its core simulator.

        We hope this was a useful evaluation. The detailed report
        is published for EDA managers who wish to make an informed
        decision of purchasing large quantity of simulators for
        their companies. Most individual users are better off just
        buying the simulator from the above information rather
        than spending $3,000 for the report.

        If you happen to quote the information from this posting,
        we request you to maintain the integrity of the information
        in tact, and credit Seva Technologies as the source.

        A VHDL simulator evaluation is near completion, and FPGA based
        synthesis tools evaluation is planned for.

        If you care to voice your opinion, we would like to know what
        you thought of SEI criteria and weights for Verilog simulators
        (VHDL are similar, and will be published in July issue of
        ASIC & EDA magazine).

        The designs we used for performance measurements were received
        from REAL users under NDA, and most are in production. If you
        would like your design to be part of a comprehensive evaluation
        process, we would certainly welcome your participation.

        Please read the articles in ASIC & EDA and EETimes.

        Thank you for your interest. We look forward to your comments
        directly by email to,, and

        If you are in Europe, you may contact Mr. Jon Howes, NEuW, for
        the availability of the report. His coordinates are:

        Jon C Howes  CIS: 100120,2101 Japan:SGS0220
        NEuW Limited, PO Box 8, Greenfield Innovation Centre,Greenfield,Oldham,
        OL3 7LZ, UK  Tel:+44 (0) 457 820 326  Fax:+44 (0) 457 820 304

Subject: G05: What is the best workstation simulator?

   The answer, of coarse, depends on what you are looking for. However,
   Yatin Trivedi has made available a summary of an evaluation of the
   workstation based verilog simulators currently available:

SEVA Technologies, Inc. co-founders Yatin Trivedi and Larry
Saunders, well-known industry consultants, organized and conducted these
evaluations, third in an ongoing series.  The evaluations are based on the
SEVA Evaluation Index (SEI), which is a comprehensive set of evaluation
criteria developed by SEVA.  The relative importance of the criteria is
derived from inputs of end users/designers, project managers at system
houses, and EDA tool developers.  The SEI is continually refined with
inputs received from previous Verilog and VHDL evaluations. Besides
raw performance, the index is weighted by measures such as language
compliance, debugging capability, integration with the design
environment, programming language interface (PLI), ability to handle a
design's timing data (SDF), product documentation, installation and
licensing, and technical support.

SEVAFs evaluation criteria and results, including the SEI distribution
and ranking based on the SEI, are summarized below.

SEI Criteria            Weight          Vendor          SEI Score
Performance             50              Chronologic     82.14
(Compile+Run+Memory)                    Cadence         69.31
Language Compliance     20              Intergraph      47.24
Debug Commands          10              Simucad         36.86
Design Env Integration   6              CAD Artisans    23.49
PLI Support              6              Wellspring      23.15
SDF and Timing           6              interHDL        22.96
Documentation &          2
Technical Support

An article outlining the evaluation results are published in the March,
1995 issue of "Integrated System Design" magazine.  Complete results
and the details of the evaluation methodology can be obtained by
subscribing to SEVA's Newsletter The Ultimate EDA Tool.

Subject: G06: Is there a vgrind def file?

   Yes. Available in the archives as:
Subject: G07: Is there a free verilog parser available?

   Yes. There are two known public domain parsers.
       This one was donated by Frank Bennett (fwb@hpfcso.FC.HP.COM).
       Here's what Frank had to say about it:
     hdl.y below is a verilog parser written using the Unix utility -
     yacc. It by no means is a complete verilog parser. This only
     represents a few nights of effort in front of the ole PC. This is
     donated in the hope that this will enable additional work by
     individuals interested in learning verilog & yacc.
       The second is from Michael A. Riepe ( Here's
       what he had to say about it:
     I ran across a verilog-HDL parser authored by It is available by anonymous FTP from in directory /pub/stcheng/vl2mv.tar.Z. It is part of
     a verilog->bliff translator. It comes complete with a wrapper for
     the translator, and contains the parser and code to build the parse
     tree. One of the handiest things is a traverse routine which echoes
     the input file back to the output by traversing the data structures,
     thus giving you a template to base your own application on.
     The parser itself seems to contain most of the verilog-HDL grammar,
     though many behavioral constructs are unimplemented in the data
     structure routines. It is still under development, so there are
     bugs. I spent a few days hacking the code and removed a lot of hooks
     to berkeley OCTTOOLS code that wasn't included with the
     distribution. The code as I downloaded it didn't compile. I'll place
     this on the anonymous FTP site here ( in
     people/riepe) - you'll get a version that compiles (at least it does
     on my decstation) and a list of bug fixes that have been sent to me
     other people I've given it to.
     Bug reprts/fixes should be sent both to, and (the author of the original version)
Subject: G08: Is there a free Verilog simulator?

   There is a free, copylefted Verilog simulator called "vbs", written by
   Jimen Ching and Lay Hoon Tho as a senior design project in the
   electrical engineering curriculum of the University of Hawaii, College
   of Engineering.
   It is available from the archive at:
     * FTP:
   It appears that Veriwell/386 and Veriwell/Sparc are now shareware. Use
   is free for source files under 1000 lines. For larger files, a
   hardware dongle is required for the MS-DOS version, a license for the
   Sparc version. The simulator is available for downloading from the
   Wellspring Solutions BBS or via ftp:
     * BBS: 1-508-865-1113 (8-N-1)
     * FTP:
   InterHDL also has shareware version. Eli Sternheim says "This is a
   full Verilog simulator with the following exceptions: no PLI, specify
   blocks are ignored, no switch level constructs but gates and
   primitives are supported. Also there is a size limitation on the
     * FTP:
   InterHDL's simulator can also be had through their mailserver. send an
   e-mail to with the word "help" in the body of the
Subject: G09: Is there a Verilog test suite?

   [contributed by Rich Kolb ]
   The OVI Test and Compliance Committee has acquired Verilog HDL tests
   and organized them into a test suite. Most of the tests are very small
   "atomic" tests that test one particular portion of the language. Each
   test consists of the Verilog circuit file and the simulation output
   file produced by OVISIM. OVISIM is the Verilog clone produced by
   Cadence and contributed to OVI.
   To induce organizations to contribute additional tests, the entire
   test suite is available to anyone who contributes 25 tests or tests
   with at least 1000 lines of Verilog code. Currently there are more
   than 400 tests in the test suite (9/12/84). Naturally, OVI would
   appreciate it if even more tests were submitted. OVI would like to see
   as many tests shared by the Verilog community as possible.
   The test submission system is set up to automatically function by
   e-mail. Tests can be mailed to the test system and it will run the
   simulations and send back the results.
   OVI welcomes all contributed tests. If a developer is only interested
   in the simulation results from a single circuit, that circuit can be
   sent to the test system and the simulation results will be returned.
   For more information on the test submission format and procedure, send
   mail to
Subject: G10: Where can I find a free Verilog quick reference card?

   In the archive, of coarse! A postscript quick reference card has been
   donated by Rajeev Madhavan. It is available in the archive:
Subject: G11: Are there related Web sites?

   Here are some links to Verilog related sites:
   Cadmazing's DA-Related Information on the Web

   EE Times

   Electronic Design Automation Companies

   IVC (International Verilog Conference)

   DAC (Design Automation Conference)

Subject: A01: Verilog vendors and products

   Caveat: Many of these product descriptions were written by the vendor.
   They may contain hype.
   Alta Group (formerly Comdisco Systems) of Cadence Design Systems
   Alternative System Concepts, Inc.
   Attest Software Inc.
   Cadence Design Systems, Inc.
   Caesium Inc.
   Chronologic Simulation
   Design Acceleration, Inc.
   DS Diagonal Systems Inc.
   Fintronic USA, Inc.
   FrontLine Design Automation Inc.
   i-Logix Inc.
   Intellitech Corporation
   Intergraph Electronics
   interHDL, Inc.
   Library Technologies, Inc.
   Precedence Incorporated
   Pragmatic C Software Corp.
   SpeedSim, Inc.
   Sunrise Test Systems
   Synopsys Inc
   Systems Science Inc.
   Verilog Consulting Service
   Veritools Inc.
   Vista Technologies, Inc.
   Wellspring Solutions, Inc.
          Alta Group (formerly Comdisco Systems) of Cadence Design
          919 E. Hillsdale Blvd. Suite #300
          Foster City, CA 94404
          Phone: (415) 574-5800
          FAX: (415) 358-3601
          Hardware Design System (HDS)
          The Hardware Design System (HDS) is a companion product to
          Alta's Signal Processing Worksystem (SPW). Designers of DSP,
          Communication and Multimedia systems use SPW/HDS to capture and
          analyze algorithms and behavior at the system level. Once the
          behavior/algorithm is verified, designers proceed to define the
          Hardware Architecture of their system using a powerful set of
          parameterized architectural blocks.
          HDS includes a library-based HDL generator which generates
          optimized Verilog (VHDL) code, targetted for specific synthesis
          tools. In addition, HDS includes an HDL-Import capability,
          which allows designers to co-simulate system-level diagrams
          with Verilog (VHDL) code.
          SPARC, HP700, IBM RS600
          Alternative System Concepts, Inc.
          P.O BOX 128
          Windham, NH 03087 USA
          Phone: (603) 437-2234
          FAX: (603) 437-2722
          verilog2vhdl translates Verilog HDL to IEEE1076-1987 compliant
          VHDL using the Standard Logic 1164 package. The present form of
          verilog2vhdl can perform a full structural translation and
          partial translation of RTL constructs in Verilog. The tool can
          also provide a software procedural interface to output VHDL.
          Future releases will support full RTL and behavioral
          translation of Verilog. IEEE1076-1993 compliance is also
          expected soon.
          The product will be available in the first quarter of 1995.
          SunOS 4.1.x, MS-DOS
          Attest Software Inc.
          4677 Old Ironsides Drive, Suite 100
          Santa Clara CA 95054
          Phone: (408) 982-0244
          FAX: (408) 982-0248
          TDX (R)
          TDX is a high-performance, interactive fault simulation and
          automatic test generation software system for Verilog.
          The software is built around a high-performance concurrent
          fault simulator that supports all of the unidirectional
          primitives, wire types, and gate/net delays defined in the
          Verilog 2.0 LRM. UDPs are also supported, along with optimized
          built-in models for single and multi-port RAMs.
          It is not necessary to sacrifice accuracy for fast fault
          The software supports the detailed pin timing and strobing
          features found on "tester-per-pin" ATE.
          TDX_FSIM - highly accurate, fast fault simulator with full
          timing and states/strengths.
          TDX_IDDQ - flexible, programmable transistor-short fault
          simulation and vector selection for current measurement
          TDX_STEP (TM) - static and dynamic testability analysis, and
          test improvement program that supports both scan and non-scan
          TDX_ATG - sequential test generation for scan and non-scan
          designs. Tightly integrated with tdx_fsim, tdx_step, and
          Free demo executables are available by anonymous ftp from
 The demo software runs on
          any small circuit, and also on an 8085 microprocessor clone
          model that is available at the ftp site.
          Sun Sparc, HP PA-RISC, and Windows NT.
          Cadence Design Systems, Inc.
          555 River Oaks Parkway
          San Jose, CA 95134
          Phone: (408) 943-1234
          Fax: (408) 943-0513
          email: ?
          The industry standard Verilog simulator.
          most workstations
          CAESIUM, Inc.
          3542 Earl Drive
          Santa Clara, CA 95051
          Phone: (408) 492 9511
          (408) 248 4603
          Fax: (408) 248 6012
          Verilog HDL Model Libraries (Custom VLSI & ASIC model
          CAESIUM, Inc. provides Verilog HDL Model Libraries.
          CAESIUM works with the customer to provide all the 'Missing
          Models' (sm) for the customer's current and next projects.
          Features Include:
         1. Full Function.
         2. Accurate Timing.
         3. Synthesizable.
         4. Intelligent X-handling.
         5. Verilog HDL Source Code models.
         6. Fast Execution.
         7. Low Cost.
          ABT, ACT, ALS, AS, BCTTTL, HCT, F, S, LS Series Glue logic
          FIFOs, MEMORIES and PAL models are available for some families,
          others can readily be developed on needed basis.
          Partial Function or Bus Function Models can be developed at a
          nominal cost.
          Models will work under LRM compatible Verilog simulators.
          Verilog-XL, VCS, SILOS III, Viper, etc.
          Chronologic Simulation
          5150 El Camino Real
          Los Altos, CA 94022
          Phone: (800) VERILOG or (415) 965-3312
          FAX: (415) 965-2705
          VCS, Verilog Compiled Simulator
          Product is a Verilog Compiler offering 10x speed improvement on
          behavioural code, and 1/10 memory usage; all as compared to
          Verilog-XL 1.6. Supports the complete language, as well as
          interactive debugging. Also supports SDF and the full PLI, and
          offers incremental compilation. Compiles to machine code on
          Sparc and HP machines, compiles to C on others.
          Sparc SunOS, Sparc Solaris, HP PA-RISC, SGI, IBM RS6000, Sony
          NeWS, DEC Alpha
          VMC, Verilog Model Compiler
          Product takes Verilog HDL source models and compiles them to C
          object modules for use with VCS, Verilog-XL and other Verilog &
          VHDL simulators. Allows component builders to release high
          performance, low memory, proprietary models to their customers
          - as object form - ie providing a very attractive alternative
          to source protection/encryption.
          Sparc SunOS, Sparc Solaris, HP PA-RISC
          Design Acceleration, Inc.

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